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| Advance Information MPC8241EC/D Rev. 3, 5/2003 MPC8241 Integrated Processor Hardware Specifications The MPC8241 combines a MPC603e PowerPCTM core microprocessor with a PCI bridge. The PCI support on the MPC8241 will allow system designers to rapidly design systems using peripherals already designed for the PCI and other standard interfaces. The MPC8241 also integrates a high-performance memory controller which supports various types of ROM and SDRAM. The MPC8241 is the second of a family of products that provides system-level support for industry standard interfaces with a MPC603e processor core. This document describes pertinent electrical and physical characteristics of the MPC8241. The MPC8241 is based on the MPC8245 design, so for functional characteristics of the processor, refer to the MPC8245 Integrated Processor User's Manual (MPC8245UM/D). This document contains the following topics: Topic Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "Package Description" Section 1.6, "PLL Configuration" Section 1.7, "System Design Information" Section 1.8, "Document Revision History" Section 1.9, "Ordering Information" Page 1 3 5 6 32 39 44 54 55 To locate any published errata or updates for this document, refer to the web site at http://www.motorola.com/semiconductors. 1.1 Overview The MPC8241 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar MPC603e core, as shown in Figure 1. Overview MPC8241 Additional Features: * Prog I/O with Watchpoint * JTAG/COP Interface * Power Management Processor Core Block Processor PLL Branch Processing Unit (BPU) (64-Bit) Two-Instruction Fetch Instruction Unit (64-Bit) Two-Instruction Dispatch System Register Unit (SRU) Integer Unit (IU) Load/Store Unit (LSU) FloatingPoint Unit (FPU) 64-Bit Data MMU 16-Kbyte Data Cache Instruction MMU 16-Kbyte Instruction Cache Peripheral Logic Bus Peripheral Logic Block Message Unit (with I2O) DMA Controller Address (32-Bit) Central Control Unit Performance Monitor I2 C I2C Controller PIC Interrupt Controller/ Timers DUART DLL Peripheral Logic PLL Configuration Registers PCI Bus Interface Unit Address Translator PCI Arbiter Data (64-Bit) Data Path ECC Controller Data Bus (32- or 64-Bit) with 8-Bit Parity or ECC Memory/ROM/ Port X Control/Address Memory Controller SDRAM_SYNC_IN SDRAM Clocks PCI_SYNC_IN 5 IRQs/ 16 Serial Interrupts Watchpoint Facility Fanout Buffers OSC_IN PCI Bus Clocks 32-Bit PCI Interface Five Request/Grant Pairs Figure 1. MPC8241 Block Diagram 2 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Features The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART), memory controller, DMA controller, PIC interrupt controller, a message unit (and I2O interface), and an I2C controller. The processor core is a full-featured, high-performance processor with floating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. The MPC8241 contains an internal peripheral logic bus that interfaces the processor core to the peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade-off performance for power consumption. The processor core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8241 memory space are passed to the processor bus for snooping when snoop mode is enabled. The processor core and peripheral logic are general-purpose in order to serve a variety of embedded applications. The MPC8241 can be used as either a PCI host or PCI agent controller. 1.2 * Features Processor core -- High-performance, superscalar processor core -- Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit (LSU), system register unit (SRU), and a branch processing unit (BPU) -- 16-Kbyte instruction cache -- 16-Kbyte data cache -- Lockable L1 caches--entire cache or on a per-way basis up to three of four ways -- Dynamic power management--supports 60x nap, doze, and sleep modes Peripheral logic -- Peripheral logic bus - Supports various operating frequencies and bus divider ratios - 32-bit address bus, 64-bit data bus - Supports full memory coherency - Decoupled address and data buses for pipelining of peripheral logic bus accesses - Store gathering on peripheral logic bus-to-PCI writes -- Memory interface - Supports up to 2 Gbytes of SDRAM memory - High-bandwidth data bus (32- or 64-bit) to SDRAM - Programmable timing supporting SDRAM - Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices - Write buffering for PCI and processor accesses - Supports normal parity, read-modify-write (RMW), or ECC - Data-path buffering between memory interface and processor Major features of the MPC8241 are as follows: * MOTOROLA MPC8241 Integrated Processor Hardware Specifications 3 Features * - Low-voltage TTL logic (LVTTL) interfaces - 272 Mbytes of base and extended ROM/Flash/Port X space - Base ROM space supports 8-bit data path or same size as the SDRAM data path (32- or 64-bit) - Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path - Port X: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects -- 32-bit PCI interface Operates up to 66 MHz - PCI 2.2-compatible - PCI 5.0-V tolerance - Support for dual address cycle (DAC) for 64-bit PCI addressing (master only) - Support for PCI locked accesses to memory - Support for accesses to PCI memory, I/O, and configuration spaces - Selectable big- or little-endian operation - Store gathering of processor-to-PCI write and PCI-to-memory write accesses - Memory prefetching of PCI read accesses - Selectable hardware-enforced coherency - PCI bus arbitration unit (five request/grant pairs) - PCI agent mode capability - Address translation with two inbound and outbound units (ATU) - Some internal configuration registers accessible from PCI -- Two-channel integrated DMA controller (writes to ROM/Port X not supported) - Supports direct mode or chaining mode (automatic linking of DMA transfers) - Supports scatter gathering--read or write discontinuous memory - 64-byte transfer queue per channel - Interrupt on completed segment, chain, and error - Local-to-local memory - PCI-to-PCI memory - Local-to-PCI memory - PCI memory-to-local memory -- Message unit - Two doorbell registers - Two inbound and two outbound messaging registers - I2O message interface -- I2C controller with full master/slave support that accepts broadcast messages -- Programmable interrupt controller (PIC) - Five hardware interrupts (IRQs) or 16 serial interrupts - Four programmable timers with cascade -- Two (dual) universal asynchronous receiver/transmitters (UARTs) 4 MPC8241 Integrated Processor Hardware Specifications MOTOROLA General Parameters * * -- Integrated PCI bus and SDRAM clock generation -- Programmable PCI bus and memory interface output drivers System level performance monitor facility Debug features -- Memory attribute and PCI attribute signals -- Debug address signals -- MIV signal: marks valid address and data bus cycles on the memory bus -- Programmable input and output signals with watchpoint capability -- Error injection/capture on data path -- IEEE 1149.1 (JTAG)/test interface 1.3 General Parameters Technology Die size Transistor count Logic design Packages Core power supply I/O power supply 0.25 m CMOS, five-layer metal 49.2 mm2 4.5 million Fully static Surface-mount 357 (thick substrate and thick mold cap) plastic ball grid array (PBGA) 1.8 V 100 mV DC (nominal; see Table 2 for details and recommended operating conditions) 3.0 to 3.6 V DC The following list provides a summary of the general parameters of the MPC8241: MOTOROLA MPC8241 Integrated Processor Hardware Specifications 5 Electrical and Thermal Characteristics 1.4 1.4.1 Electrical and Thermal Characteristics DC Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8241. This section covers ratings, conditions, and other characteristics. 1.4.1.1 Absolute Maximum Ratings This section describes the MPC8241 DC electrical characteristics. Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings Characteristic 1 Supply voltage--CPU core and peripheral logic Supply voltage--memory bus drivers PCI and standard I/O buffers Supply voltage--PLLs Supply voltage--PCI reference Input voltage 2 Operational die-junction temperature range Storage temperature range Symbol VDD GVDD_OVDD AVDD/AVDD2 LVDD Vin Tj Tstg Range -0.3 to 2.1 -0.3 to 3.6 -0.3 to 2.1 -0.3 to 5.4 -0.3 to 3.6 0 to 105 -55 to 150 Unit V V V V V C C Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. PCI inputs with LVDD = 5 V 5% V DC may be correspondingly stressed at voltages exceeding LVDD + 0.5 V DC. 1.4.1.2 Recommended Operating Conditions Table 2. Recommended Operating Conditions Characteristic Symbol VDD GVDD_OVDD AVDD AVDD2 LVDD Recommended Value 1.8 100 mV 3.3 1.8 1.8 Unit V V Notes 1, 2 2 1, 2 V V V 1, 2 4, 5, 6 5, 6, 7 Table 2 provides the recommended operating conditions for the MPC8241. Supply voltage I/O buffer supply for PCI and standard; supply voltages for memory bus drivers CPU PLL supply voltage PLL supply voltage--peripheral logic PCI reference 0.3 100 mV 100 mV 5% 0.3 5.0 3.3 6 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Input voltage PCI inputs All other inputs Die-junction temperature Tj Symbol Vin Recommended Value 0 to 3.6 or 5.75 0 to 3.6 0 to 105 Unit V V C Notes 4, 7 8 Notes: 1. CPU speed limited to 266 MHz operation at this voltage. See Table 7. 2. Caution: GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset. Note that GVDD_OVDD pins are all shorted together: This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. Connections should not be made to individual PWRRING pins. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: VDD/AVDD/AVDD2 must not exceed GVDD_OVDD by more than 0.6 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 5.0 V DC power supply. 5. Caution: LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. Caution: LVDD must not exceed GVDD_OVDD by more than 3.0 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3 V DC power supply. 8. Caution: Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5 V at all times including during power-on reset. Input voltage (Vin) must not be greater than GVDD_OVDD by more than 0.6 V at all times including during power-on reset. MOTOROLA MPC8241 Integrated Processor Hardware Specifications 7 Electrical and Thermal Characteristics Figure 2 shows supply voltage sequencing and separation cautions. DC Power Supply Voltage 5V 6 5 See Note 1 LVDD @ 5 V 3.3 V 2V 3 6 5 2 GVDD_OVDD/(LVDD @ 3.3 V - - - -) VDD/AVDD/AVDD2 VDD Stable 100 s PLL Relock Time 3 0 Voltage Regulator Delay 2 Power Supply Ramp Up 2 HRST_CPU and HRST_CTRL Asserted 255 External Memory Clock Cycles 3 Time Reset Configuration Pins 9 External Memory Clock Cycles Setup Time 4 HRST_CPU and HRST_CTRL Maximum Rise Time Must be Less Than One External Memory Clock Cycle 5 VM = 1.4 V Notes: 1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2. 2. Refer to Section 1.7.2, "Power Supply Sizing," for additional information on this topic. 3. Refer to Table 8 for additional information on PLL relock and reset signal assertion timing requirements. 4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements. 5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device to be in the nonreset state. Figure 2. Supply Voltage Sequencing and Separation Cautions 8 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Figure 3 shows the undershoot and overshoot voltage of the MPC8241memory interface. 4V VIH GVDD_OVDD + 5% GVDD_OVDD VIL GND/GNDRING GND/GNDRING - 0.3 V GND/GNDRING - 1.0 V Not to Exceed 10% of tSDRAM_CLK Figure 3. Overshoot/Undershoot Voltage Figure 4 and Figure 5 show the undershoot and overshoot voltage of the MPC8241 PCI interface for 3.3and 5-V signals, respectively. 11 ns (Min) +7.1 V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform -3.5 V 7.1 V p-to-p (Min) 7.1 V p-to-p (Min) 4 ns (Max) Figure 4. Maximum AC Waveforms for 3.3-V Signaling MOTOROLA MPC8241 Integrated Processor Hardware Specifications 9 Electrical and Thermal Characteristics 11 ns (Min) +11 V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +5.25 V Undervoltage Waveform -5.5 V 10.75 V p-to-p (Min) 11 V p-to-p (Min) 4 ns (Max) Figure 5. Maximum AC Waveforms for 5-V Signaling 1.4.1.3 DC Electrical Characteristics Table 3. DC Electrical Specifications Table 3 provides the DC electrical characteristics for the MPC8241 at recommended operating conditions. Characteristics Input high voltage Input low voltage Input high voltage Input low voltage PCI_SYNC_IN input high voltage PCI_SYNC_IN input low voltage Conditions PCI only PCI only All other pins (GVDD_OVDD = 3.3 V) All inputs except PCI_SYNC_IN Symbol VIH VIL VIH VIL CVIH CVIL IL Min 0.65 x GVDD_OVDD -- 2.0 GND/GNDRING 2.4 GND/GNDRING -- Max LVDD 0.3 x GVDD_OVDD 3.3 0.8 -- 0.4 70 Unit V V V V V V A Notes 1 2 2 3 Input leakage current 0.5 V Vin 2.7 V for pins using DRV_PCI @ LVDD = 4.75 V driver Input leakage current all LVDD = 3.6 V others GVDD_OVDD 3.465 V Output high voltage Output low voltage IOH = driver dependent (GVDD_OVDD = 3.3 V) IOL = driver dependent (GVDD_OVDD = 3.3 V) IL VOH VOL -- 2.4 -- 10 -- 0.4 A V V 3 4 4 10 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Table 3. DC Electrical Specifications (continued) Characteristics Capacitance Conditions Vin = 0 V, f = 1MHz Symbol Cin Min -- Max 15.0 Unit pF Notes Notes: 1. See Table 17 for pins with internal pull-up resistors. 2. All grounded pins are connected together. 3. Leakage current is measured on input and output pins in the high-impedance state. The leakage current is measured for nominal GVDD_OVDD/LVDD and VDD or both GVDD_OVDD/LVDD and VDD must vary in the same direction. 4. See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 17. 1.4.1.4 Output Driver Characteristics Table 4 provides information on the characteristics of the output drivers referenced in Table 17. The values are preliminary estimates from an IBIS model and are not tested. Table 4. Drive Capability of MPC8241 Output Pins 5, 6 Driver Type Programmable Output Impedance () 20 40 (default) DRV_PCI 20 40 (default) DRV_MEM_CTRL DRV_PCI_CLK DRV_MEM_CLK 6 (default) 20 40 Supply Voltage IOH 36.6 18.6 12.0 6.1 89.0 36.6 18.6 IOL 18.0 9.2 12.4 6.3 42.3 18.0 9.2 Unit Notes DRV_STD_MEM GVDD_OVDD = 3.3 V mA mA mA mA mA mA mA 2, 4 2, 4 1, 3 1, 3 2, 4 2, 4 2, 4 Notes: 1. For DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33-V label by interpolating between the 0.3- and 0.4-V table entries current values which corresponds to the PCI VOH = 2.97 = 0.9 x GVDD_OVDD (GVDD_OVDD = 3.3 V) where table entry voltage = GVDD_OVDD - PCI VOH. 2. For all others with GVDD_ OVDD = 3.3 V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.9-V table entry which corresponds to the VOH = 2.4 V where table entry voltage = GVDD_OVDD - VOH. 3. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33 V = PCI VOL = 0.1 x GVDD_OVDD (GVDD_OVDD = 3.3 V) by interpolating between the 0.3- and 0.4-V table entries. 4. For all others with GVDD_OVDD = 3.3 V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4-V table entry. 5. See driver bit details for output driver control register (0x73) in the MPC8245 Integrated Processor User's Manual. 6. See Chip Errata No. 19 in the MPC8245/MPC8241 Integrated Processor Chip Errata. MOTOROLA MPC8241 Integrated Processor Hardware Specifications 11 Electrical and Thermal Characteristics 1.4.1.5 Power Characteristics Table 5. Preliminary Power Consumption PCI Bus Clock/Memory Bus Clock CPU Clock Frequency (MHz) Table 5 provides preliminary estimated power consumption data for the MPC8241. Mode 33/66/ 133 Typical Max--CFP Max--INT Doze Nap Sleep 0.7 0.8 0.8 0.5 0.2 0.2 33/66/ 166 0.8 1.0 0.9 0.6 0.2 0.2 33/66/ 200 1.0 1.2 1.0 0.7 0.3 0.2 33/100/ 200 1.0 1.3 1.2 0.8 0.4 0.2 66/100/ 200 1.0 1.3 1.2 0.8 0.4 0.3 66/66/ 266 1.5 1.9 1.6 1.0 0.4 0.2 66/133/ 266 1.8 2.1 1.8 1.3 0.7 0.4 Unit Notes W W W W W W 1, 5 1, 2 1, 3 1, 4, 6 1, 4, 6 1, 4, 6 I/O Power Supplies 7 Mode GVDD_OVDD Minimum 500 Maximum 1100 Unit mW Notes 8 Notes: 1. The values include VDD, AVDD, and AVDD2 but do not include I/O supply power, see Section 1.7.2, "Power Supply Sizing," for information on GVDD_OVDD supply power. 2. Maximum--FP power is measured at VDD = 1.9 V with dynamic power management enabled while running an entirely cache-resident, looping, floating-point multiplication instruction. 3. Maximum--INT power is measured at VDD = 1.9 V with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. Power saving mode maximums are measured at VDD = 1.9 V while the device is in doze, nap, or sleep mode. 5. Typical power is measured at VDD = AVDD = 1.8 V, GVDD_OVDD = 3.3 V where a nominal FP value, a nominal INT value, and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory are averaged. 6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled. 7. Power consumption of PLL supply pins (AVDD and AVDD2) < 15 mW, guaranteed by design, but not tested. 8. The typical maximum GVDD_OVDD value resulted from the MPC8241 operating at the fastest frequency combination of 66:100:200 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros to PCI memory and on 64-bit boundaries to local memory. 12 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics 1.4.2 Thermal Characteristics Table 6 provides the package thermal characteristics for the MPC8241. For further information, see Section 1.7.8, "Thermal Management Information." Table 6. Thermal Characterization Data Value 7 (166- and 200-MHz Parts) 38 25 31 22 17 8 2 Value 7 (266-MHz Part) 28 20 22 17 11 7 2 Rating Board Description Symbol Unit Notes Junction-to-ambient natural convection Junction-to-ambient natural convection Junction-to-ambient (@200 ft/min) Junction-to-ambient (@200 ft/min) Junction-to-board (bottom) Junction-to-case (top) Junction-to-package top Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) Four-layer board (2s2p) Single-layer board (1s) Natural convection RJA RJMA RJMA RJMA RJB RJC JT C/W C/W C/W C/W C/W C/W C/W 1, 2 1, 3 1, 3 1, 3 4 5 6 Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and EIA/JESD51-2 with the board horizontal. 3. Per EIA/JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per EIA/JESD51-2. 7. Note that the 166- and 200-MHz parts are in a two-layer package and the 266-MHz part is in a four-layer package. This results in different thermal characterization data for the two package types. 1.4.3 AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC8241. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Table 7 and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core frequency. See Section 1.9, "Ordering Information." Table 7 provides the operating frequency information for the MPC8241 at recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V. MOTOROLA MPC8241 Integrated Processor Hardware Specifications 13 Electrical and Thermal Characteristics Table 7. Operating Frequency 166 MHz Characteristic Min Processor frequency (CPU) Memory bus frequency PCI input frequency 100 33 Max 166 83 200 MHz VDD/AVDD/AVDD2 = 1.8 100 mV Min 100 33 25-66 Max 200 100 Min 100 33 Max 266 133 MHz MHz MHz 266 MHz Unit Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.6, "PLL Configuration," for valid PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies. 1.4.3.1 Clock AC Specifications Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in Section 1.4.3.2, "Input AC Timing Specifications." These specifications are for the default driver strengths indicated in Table 4. Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled number items listed in Table 8. Table 8. Clock AC Timing Specifications At recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V Num 1a 2, 3 4 5a 5b 7 8a 8b 10 15 16 17 19 20 Characteristics and Conditions Frequency of operation (PCI_SYNC_IN) PCI_SYNC_IN rise and fall times PCI_SYNC_IN duty cycle measured at 1.4 V PCI_SYNC_IN pulse width high measured at 1.4 V PCI_SYNC_IN pulse width low measured at 1.4 V PCI_SYNC_IN jitter PCI_CLK[0:4] skew (pin-to-pin) SDRAM_CLK[0:3] skew (pin-to-pin) Internal PLL relock time DLL lock range with DLL_EXTEND = 0 disabled (default) DLL lock range with DLL_EXTEND = 1 enabled Frequency of operation (OSC_IN) OSC_IN rise and fall times OSC_IN duty cycle measured at 1.4 V Min 25 -- 40 6 6 -- -- -- -- Max 66 2.0 60 9 9 150 250 190 100 Unit MHz ns % ns ns ps ps ps s ns ns MHz ns % Notes 1 2 2 3 2, 4, 5 6 6 (N x Tclk - Tdp(max)) Tloop (N x Tclk - Tdp(min)) ((N - 0.5) x Tclk - Tdp(max)) Tloop ((N - 0.5) x Tclk - Tdp(min)) 25 -- 40 66 5 60 7 14 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications (continued) At recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V Num 21 Characteristics and Conditions OSC_IN frequency stability Min -- Max 100 Unit ppm Notes Notes: 1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V. 2. Specification value at maximum frequency of operation. 3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew between SDRAM_CLKs can be measured, the relationship between the internal sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design. 4. Relock time is guaranteed by design and characterization. Relock time is not tested. 5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence. 6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figure 7 through Figure 10). Tclk is the period of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagation delay of the DLL synchronization feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. Tdp(max) and Tdp(min) are dependent on tap delay. See Table 9 for values of Tdp(max) and Tdp(min). See Figure 7 through Figure 10 for DLL locking ranges. Refer to Motorola Application Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more details on memory clock design. 7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are not tested. Figure 6 shows the PCI_SYNC_IN input clock timing diagram and Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation. 1 5a 5b 2 3 CVIH PCI_SYNC_IN VM VM VM CVIL VM = Midpoint Voltage (1.4 V) Figure 6. PCI_SYNC_IN Input Clock Timing Diagram Table 9 lists the values of Tdp(min) and Tdp(max). Table 9. Tdp(min) and Tdp(max) Mode Normal tap delay: bit 2 (DLL_MAX_DELAY) at offset 0x76 is cleared Maximum tap delay: bit 2 (DLL_MAX_DELAY) at offset 0x76 is set Tdp(min) 7.58 8.28 Tdp(max) 12.97 17.57 Unit ns ns Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation. These graphs define the areas of DLL locking for various modes. The grey areas represent where the DLL will lock. 15 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Note also that the DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished by increasing the time between each of the 128 tap points in the delay line. Although this increased time makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock between adjacent tap points. Refer to Motorola Application Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more details on memory design. 30 27.5 N=1 25 22.5 Tclk SDRAM_SYNC_OUT Period (ns) 20 17.5 15 12.5 10 N=2 7.5 0 1 2 Tloop Propagation Delay Time (ns) 3 4 Figure 7. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1 and Normal Tap Delay 16 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics 30 27.5 N=1 25 22.5 Tclk SDRAM_SYNC_OUT Period (ns) 20 17.5 15 12.5 N=2 10 7.5 0 1 2 Tloop Propagation Delay Time (ns) 3 4 Figure 8. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1 and Tap Max Delay 17 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics 25 22.5 20 Tclk SDRAM_SYNC_OUT Period (ns) 17.5 15 N=1 12.5 10 N=2 7.5 0 1 2 Tloop Propagation Delay Time (ns) 3 4 Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0 and Normal Tap Delay 18 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics 25 22.5 20 Tclk SDRAM_SYNC_OUT Period (ns) N=1 17.5 15 12.5 10 N=2 7.5 0 1 2 Tloop Propagation Delay Time (ns) 3 4 Figure 10. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0 and Max Tap Delay 1.4.3.2 Input AC Timing Specifications Table 10 provides the input AC timing specifications at recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V. See Figure 11 and Figure 12. 19 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Table 10. Input AC Timing Specifications Num 10a 10b 10b0 10b1 10b2 10b3 10c 10d 10e 11 11a 11a0 11a1 11a2 11a3 11b 11c Characteristic PCI input signals valid to PCI_SYNC_IN (input setup) Memory input signals valid to SDRAM_SYNC_IN (input setup) Tap 0, register offset <0x77>, bits 5:4 = 0b00 Tap 1, register offset <0x77>, bits 5:4 = 0b01 Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default) Tap 3, register offset <0x77>, bits 5:4 = 0b11 PIC, misc. debug input signals valid to SDRAM_SYNC_IN (input setup) I2C input signals valid to SDRAM_SYNC_IN (input setup) Mode select inputs valid to HRST_CPU/HRST_CTRL (input setup) Tos--SDRAM_SYNC_IN to sys_logic_clk offset time SDRAM_SYNC_IN to memory signal inputs invalid (input hold) Tap 0, register offset <0x77>, bits 5:4 = 0b00 Tap 1, register offset <0x77>, bits 5:4 = 0b01 Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default) Tap 3, register offset <0x77>, bits 5:4 = 0b11 HRST_CPU/HRST_CTRL to mode select inputs invalid (input hold) PCI_SYNC_IN to inputs invalid (input hold) 0 0.7 1.4 2.1 0 1.0 -- -- -- -- -- -- ns ns 2, 3, 5 1, 2, 3 ns 2, 3, 6 2.6 1.9 1.2 0.5 3.0 3.0 9 x tCLK 0.65 -- -- -- -- -- -- -- 1.0 ns ns ns ns 2, 3 2, 3 2, 3-5 7 ns 2, 3, 6 Min 3.0 Max -- Unit ns Notes 1, 3 Notes: 1. All PCI signals are measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 x GVDD_OVDD of the signal in question for 3.3-V PCI signaling levels. See Figure 12. 2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the VM = 1.4 V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 11. 3. Input timings are measured at the pin. 4. tCLK is the time of one SDRAM_SYNC_IN clock cycle. 5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 13. 6. The memory interface input setup and hold times are programmable to four possible combinations by programming bits 5:4 of register offset <0x77> to select the desired input setup and hold times. 7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM clocks become offset by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened by this amount relative to the SDRAM clock output trace lengths to maintain phase-alignment of the memory clocks with respect to sys_logic_clk. Note that the DLL locking range graphs of Figure 7 through Figure 10 compensate for Tos and there is no additional requirement to shorten Tloop by the duration of Tos. Refer to Motorola Application Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more details on accommodating for the problem of Tos and trace measurements in general. 20 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics PCI_SYNC_IN VM sys_logic_clk Tos VM VM VM SDRAM_SYNC_IN (After DLL Locks if no compensation for TOS is made) Shown in 2:1 Mode VM 10b-d 11a 12b-d 13b 14b 2.0 V Memory Inputs/Outputs 0.8 V Input Timing 2.0 V 0.8 V Output Timing Notes: VM = midpoint voltage (1.4 V). 10b-d = input signals valid timing. 11a = input hold time of SDRAM_SYNC_IN to memory. 12b-d = SDRAM_SYNC_IN to output valid timing. 13b = output hold time for non-PCI signals. 14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals. Tos = offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to be seen before sys_logic_clk once the DLL locks, if no other accommodation is made for the delay. Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN PCI_SYNC_IN GVDD_OVDD 2 10a GVDD_OVDD 2 GVDD_OVDD 2 12a 13a 14a 11c PCI Inputs/Outputs 0.4 x GVDD_OVDD GVDD_OVDD x 0.615 0.285 Input Timing Output Timing Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN 21 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics HRST_CPU/HRST_CTRL VM 10e 11b Mode Pins 2.0 V 0.8 V VM = Midpoint Voltage (1.4 V) Figure 13. Input Timing Diagram for Mode Select Signals 1.4.3.3 Output AC Timing Specification Table 11 provides the processor bus AC timing specifications for the MPC8241 at recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V. See Figure 11. All output timings assume a purely resistive 50- load (see Figure 14). Output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. These specifications are for the default driver strengths indicated in Table 4. Table 11. Output AC Timing Specifications Num 12a 12a0 12a1 12a2 12a3 12b 12c 12d 12e 13a 13a0 13a1 13a2 13a3 13b 14a Characteristic PCI_SYNC_IN to output valid, see Figure 15 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (default) Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00 SDRAM_SYNC_IN to output valid (memory control and data signals) SDRAM_SYNC_IN to output valid (for all others) SDRAM_SYNC_IN to output valid (for I2C) SDRAM_SYNC_IN to output valid (ROM/Flash/Port X) Output hold (PCI), see Figure 15 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (default) Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00 Output hold (all others) PCI_SYNC_IN to output high impedance (for PCI) 2.0 2.5 3.0 3.5 1.0 -- -- -- -- -- -- 14.0 ns ns 2 1, 3 ns 1, 3, 4 -- -- -- -- -- -- -- -- 6.0 6.5 7.0 7.5 4.5 7.0 5.0 6.0 ns ns ns ns 2 2 2 2 ns 1, 3 Min Max Unit Notes 22 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Table 11. Output AC Timing Specifications (continued) Num 14b Characteristic SDRAM_SYNC_IN to output high impedance (for all others) Min -- Max 4.0 Unit ns Notes 2 Notes: 1. All PCI signals are measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 x GVDD_OVDD or 0.615 x GVDD_OVDD of the signal in question for 3.3 V PCI signaling levels. See Figure 12. 2. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 11. 3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP, DEVSEL, PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA. 4. In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI systems, the MPC8241 has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also affected). The initial value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals; the values on these two signals are inverted then stored as the initial settings of PCI_HOLD_DEL = PMCR2[5:4] (power management configuration register 2 <0x72>), respectively. Since MCP and CKE have internal pull-up resistors, the default value of PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration register. See Figure 15. Output Measurements are Made at the Device Pin Z0 = 50 GVDD_OVDD/2 for PCI or Memory Output RL = 50 Figure 14. AC Test Load for the MPC8241 23 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics PCI_SYNC_IN 12a2, 8.1 ns for 33 MHz PCI PCI_HOLD_DEL = 10 GVDD_OVDD/2 GVDD_OVDD/2 13a2, 2.1 ns for 33 MHz PCI PCI_HOLD_DEL = 10 PCI Inputs/Outputs 33 MHz PCI 12a0, 5.5 ns for 66 MHz PCI PCI_HOLD_DEL = 00 13a0, 1 ns for 66 MHz PCI PCI_HOLD_DEL = 00 PCI Inputs/Outputs 66 MHz PCI As PCI_HOLD_DEL Values Decrease PCI Inputs and Outputs As PCI_HOLD_DEL Values Increase Note: Diagram not to scale. Output Valid Output Hold Figure 15. PCI_HOLD_DEL Affect on Output Valid and Hold Time 24 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics 1.4.3.4 I2C AC Timing Specifications Table 12 provides the I2C input AC timing specifications for the MPC8241 at recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V. Table 12. I2C Input AC Timing Specifications Num 1 2 Characteristic Start condition hold time Clock low period (time before the MPC8241 will drive SCL low as a transmitting slave after detecting SCL low as driven by an external master) SCL/SDA rise time (from 0.5 to 2.4 V) Data hold time SCL/SDA fall time (from 2.4 to 0.5 V) Clock high period (time needed to either receive a data bit or generate a START or STOP) Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 4.0 ) x (5 - 8.0 + (16 x 2 4({FDR[5],FDR[1]} == b'10) - 3({FDR[5],FDR[1]} == b'11) - 2({FDR[5],FDR[1]} == b'00) - 1({FDR[5],FDR[1]} == b'01)) FDR[4:2] Max -- -- Unit CLKs CLKs Notes 1, 2 1, 2, 4, 5 3 4 5 6 -- 0 -- 5.0 1 -- 1 -- ms ns ms CLKs 1, 2, 5 2 7 8 9 3.0 4.0 4.0 -- -- -- ns CLKs CLKs 3 1,2 1, 2 Notes: 1. Units for these specifications are in SDRAM_CLK units. 2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times two plus one SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 17. 3. Timing is relative to the sampling clock (not SCL). 4. FDR[x] refers to the frequency divider register I2CFDR bit x. 5. Input clock low and high periods in combination with the FDR value in the frequency divider register (I2CFDR) determine the maximum I2C input frequency. See Table 13. 25 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Table 13 provides the I2C frequency divider register (I2CFDR) information for the MPC8241. Table 13. MPC8241 Maximum I2C Input Frequency Max I2C Input Frequency 1 FDR Hex 2 Divider (Dec) 2 SDRAM_CLK @ 33 MHz 1.13 MHz 733 540 428 302 234 160 122 83 62 42 31 21 16 10 8 5 4 SDRAM_CLK @ 50 MHz 1.72 MHz 1.11 MHz 819 649 458 354 243 185 125 95 64 48 32 24 16 12 8 6 SDRAM_CLK @ 100 MHz 3.44 MHz 2.22 MHz 1.63 MHz 1.29 MHz 917 709 487 371 251 190 128 96 64 48 32 24 16 12 SDRAM_CLK 4 @ 133 MHz 4.58 MHz 2.95 MHz 2.18 MHz 1.72 MHz 1.22 MHz 943 648 494 335 253 170 128 85 64 43 32 21 16 20, 21 22, 23, 24, 25 0, 1 2, 3, 26, 27, 28, 29 4, 5 6, 7, 2A, 2B, 2C, 2D 8, 9 A, B, 2E, 2F, 30, 31 C, D E, F, 32, 33, 34, 35 10, 11 12, 13, 36, 37, 38, 39 14, 15 16, 17, 3A, 3B, 3C, 3D 18, 19 1A, 1B, 3E, 3F 1C, 1D 1E, 1F 160, 192 224, 256, 320, 384 288, 320 384, 448, 480, 512, 640, 768 576, 640 768, 896, 960, 1024, 1280, 1536 1152, 1280 1536, 1792, 1920, 2048, 2560, 3072 2304, 2560 3072, 3584, 3840, 4096, 5120, 6144 4608, 5120 6144, 7168, 7680, 8192, 10240, 12288 9216, 10240 12288, 14336, 15360, 16384, 20480, 24576 18432, 20480 24576, 28672, 30720, 32768 36864, 40960 49152, 61440 Notes: 1. Values are in kHz unless otherwise specified. 2. FDR Hex and Divider (Dec) values are listed in corresponding order. 3. Multiple Divider (Dec) values will generate the same input frequency, but each Divider (Dec) value will generate a unique output frequency as shown in Table 14. 4. Only available for the 266-MHz part. 26 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics Table 14 provides the I2C output AC timing specifications for the MPC8241 at recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V. Table 14. I2C Output AC Timing Specifications Num 1 2 3 4 Characteristic Start condition hold time Clock low period SCL/SDA rise time (from 0.5 to 2.4 V) Data hold time Min (FDR[5] == 0) x (DFDR/16)/2N + (FDR[5] == 1) x (DFDR/16)/2M DFDR/2 -- 8.0 + (16 x 2FDR[4:2]) x (5 - 4({FDR[5],FDR[1]} == b'10) - 3({FDR[5],FDR[1]} == b'11) - 2({FDR[5],FDR[1]} == b'00) - 1({FDR[5],FDR[1]} == b'01)) -- DFDR/2 (DFDR/2) - (output data hold time) DFDR + (output start condition hold time) 4.0 Max -- -- -- -- Unit CLKs CLKs ms CLKs Notes 1-3 1-3 4 1-3 5 6 7 8 9 SCL/SDA fall time (from 2.4 to 0.5 V) Clock high time Data setup time (MPC8241 as a master only) Start condition setup time (for repeated start condition only) Stop condition setup time <5 -- -- -- -- ns CLKs CLKs CLKs CLKs 5 1-3 1, 3 1-3 1, 2 Notes: 1. Units for these specifications are in SDRAM_CLK units. 2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times two plus one SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 17. 3. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to Table 10-5 in the MPC8245 Integrated Processor User's Manual. FDR[x] refers to the frequency divider register I2CFDR bit x. N is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 16. M is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9. 4. Since SCL and SDA are open-drain type outputs, which the MPC8241 can only drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. 5. Specified at a nominal 50 pF load. 2 SCL VM VM 6 1 4 SDA Figure 16. I2C Timing Diagram I 27 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics 5 3 SCL VM VH VL 8 9 SDA Figure 17. I2C Timing Diagram II DFFSR Filter Clock 7 SDA Note: DFFSR filter clock is the SDRAM_CLK clock times DFFSR value. Input Data Valid Figure 18. I2C Timing Diagram III . SCL/SDArealtime VM Delay SCL/SDAqualified VM Note: The delay is the local memory clock times DFFSR times two plus one local memory clock. Figure 19. I2C Timing Diagram IV (Qualified Signal) 28 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics 1.4.3.5 PIC Serial Interrupt Mode AC Timing Specifications Table 15 provides the PIC serial interrupt mode AC timing specifications for the MPC8241 at recommended operating conditions (see Table 2) with GVDD_OVDD = 3.3 V 5% and LVDD = 3.3 V 0.3 V. Table 15. PIC Serial Interrupt Mode AC Timing Specifications Num 1 2 3 4 5 6 7 Characteristic S_CLK frequency S_CLK duty cycle S_CLK output valid time Output hold time S_FRAME, S_RST output valid time S_INT input setup time to S_CLK S_INT inputs invalid (hold time) to S_CLK Min 1/14 SDRAM_SYNC_IN 40 -- 0 -- 1 sys_logic_clk period + 2 -- Max 1/2 SDRAM_SYNC_IN 60 6 -- 1 sys_logic_clk period + 6 -- 0 Unit MHz % ns ns ns ns ns Notes 1 -- -- -- 2 2 2 Notes: 1. See the MPC8245 Integrated Processor User's Manual for a description of the PIC interrupt control register (ICR) describing S_CLK frequency programming. 2. S_RST, S_FRAME, and S_INT shown in Figure 20 and Figure 21, depict timing relationships to sys_logic_clk and S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the MPC8245 Integrated Processor User's Manual for a complete description of the functional relationships between these signals. 3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is implemented and the DLL is locked. See the MPC8245 Integrated Processor User's Manual for a complete clocking description. sys_logic_clk VM 3 VM VM 4 S_CLK VM VM 5 4 S_FRAME VM S_RST VM Figure 20. PIC Serial Interrupt Mode Output Timing Diagram 29 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics S_CLK 6 VM 7 S_INT Figure 21. PIC Serial Interrupt Mode Input Timing Diagram 1.4.3.6 IEEE 1149.1 (JTAG) AC Timing Specifications Table 16 provides the JTAG AC timing specifications for the MPC8241 while in the JTAG operating mode at recommended operating conditions (see Table 2) with LVDD = 3.3 V 0.3 V. Timings are independent of the system clock (PCI_SYNC_IN). Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) Num Characteristic TCK frequency of operation 1 2 3 4 5 6 7 8 9 10 11 12 13 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TRST setup time to TCK falling edge TRST assert time Input data setup time Input data hold time TCK to output data valid TCK to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance Min 0 40 20 0 10 10 5 15 0 0 5 15 0 0 Max 25 -- -- 3 -- -- -- -- 30 30 -- -- 15 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 3 3 1 Notes Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Nontest (other than TDI and TMS) signal input timing with respect to TCK. 3. Nontest (other than TDO) signal output timing with respect to TCK. 1 2 2 TCK 3 3 VM VM VM VM = Midpoint Voltage Figure 22. JTAG Clock Input Timing Diagram 30 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Electrical and Thermal Characteristics TCK 4 TRST 5 Figure 23. JTAG TRST Timing Diagram TCK 6 7 Data Inputs 8 Input Data Valid Data Outputs 9 Output Data Valid Data Outputs Figure 24. JTAG Boundary Scan Timing Diagram TCK 10 11 TDI, TMS 12 Input Data Valid TDO 13 Output Data Valid TDO Figure 25. Test Access Port Timing Diagram 31 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Package Description 1.5 1.5.1 Package Description Package Parameters for the MPC8241 Package Outline Interconnects Pitch Solder Balls 25 mm x 25 mm 357 1.27 mm ZQ (PBGA)--62 Sn/36 Pb/2 Ag VR (Lead free version of package)--95.5 Sn/4.0 Ag/0.5 Cu Solder Ball Diameter 0.75 mm Maximum Module Height 2.52 mm Co-planarity Specification 0.15 mm Maximum Force 6.0 lbs. total, uniformly distributed over package (8 grams/ball) This section details package parameters, pin assignments, and dimensions. The MPC8241 uses a 25 mm x 25 mm, cavity up, 357-pin plastic ball grid array (PBGA) package. The package parameters are as follows. 32 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Package Description 1.5.2 Pin Assignments and Package Dimensions Figure 26 shows the top surface, side profile, and pinout of the MPC8241, 357 PBGA package. Figure 26. MPC8241 Package Dimensions and Pinout Assignments 33 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Package Description 1.5.3 Pinout Listings Table 17. MPC8241 Pinout Listing Table 17 provides the pinout listing for the MPC8241, 357 PBGA package. Signal Name Package Pin Number Pin Type Power Supply Output Driver Type Notes PCI Interface Signals C/BE[3:0] DEVSEL FRAME IRDY LOCK AD[31:0] V11 V7 W3 R3 U6 T8 U7 V6 U13 V13 U11 W14 V14 U12 W10 T10 V10 U9 V9 W9 W8 T9 W7 V8 V4 W4 V3 V2 T5 R6 V1 T2 U3 P3 T4 R1 T3 R4 U2 U1 R7 W15 U15 W17 V12 T11 V16 U14 T15 V15 W13 T7 U5 W5 W6 T12 U10 I/O I/O I/O I/O Input I/O GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD DRV_PCI DRV_PCI DRV_PCI DRV_PCI -- DRV_PCI 1, 2 2, 3 2, 3 2, 3 3 1, 2 PAR GNT[3:0] GNT4/DA5 REQ[3:0] REQ4/DA4 PERR SERR STOP TRDY INTA IDSEL I/O Output Output Input I/O I/O I/O I/O I/O Output Input GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD DRV_PCI DRV_PCI DRV_PCI -- -- DRV_PCI DRV_PCI DRV_PCI DRV_PCI DRV_PCI -- 2 1, 2 2, 4, 5 1, 6 5, 6 2, 3, 7 2, 3, 8 2, 3 2, 3 2, 8 Memory Interface Signals MDL[0:31] M19 M17 L16 L17 K18 J18 K17 K16 J15 J17 H18 F16 H16 H15 G17 D19 B3 C4 C2 D3 G5 E1 H5 E2 F1 F2 G2 J5 H1 H4 J4 J1 M18 L18 L15 K19 K15 J19 J16 H17 G19 G18 G16 D18 F18 E18 G15 E15 C3 D4 E5 F5 D1 E4 D2 E3 F4 G3 G4 G1 H2 J3 J2 K5 A18 B18 A6 C7 D15 D14 A9 B8 I/O GVDD_OVDD DRV_STD_MEM 1, 9 MDH[0:31] I/O GVDD_OVDD DRV_STD_MEM 1 DQM[0:7] Output GVDD_OVDD DRV_MEM_CTRL 1 34 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Package Description Table 17. MPC8241 Pinout Listing (continued) Signal Name CS[0:7] FOE RCS0 RCS1 RCS2/TRIG_IN RCS3/TRIG_OUT SDMA[1:0] SDMA[11:2] DRDY SDMA12/SRESET SDMA13/TBEN SDMA14/ CHKSTOP_IN SDBA1 SDBA0 PAR[0:7] SDRAS SDCAS CKE WE AS Package Pin Number A17 B17 C16 C17 C9 C8 A10 B10 A7 C10 B9 P18 N18 A15 B15 A11 B12 A12 C12 B13 C13 D12 A14 C14 B14 P1 L3 K3 K2 C11 B11 E19 C19 D5 D6 E16 F17 B2 C1 B19 D16 C6 B16 A16 Pin Type Output I/O Output Output I/O Output I/O Output Input I/O I/O I/O Output Output I/O Output Output Output Output Output Power Supply GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD Output Driver Type DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL -- DRV_STD_MEM DRV_MEM_CTRL DRV_MEM_CTRL -- DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL DRV_STD_MEM DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL DRV_MEM_CTRL 10, 11 1 10 10 10, 11 5, 12 5 1, 10, 11 1 5, 13 5, 12 5, 12 5, 12 Notes 1 10, 11 10, 11 PIC Control Signals IRQ0/S_INT IRQ1/S_CLK IRQ2/S_RST IRQ3/S_FRAME IRQ4/L_INT P4 R2 U19 P15 P2 Input I/O I/O I/O I/O GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD -- DRV_PCI DRV_PCI DRV_PCI DRV_PCI 35 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Package Description Table 17. MPC8241 Pinout Listing (continued) Signal Name Package Pin Number Pin Type Power Supply Output Driver Type Notes I2C Control Signals SDA SCL P17 R19 I/O I/O GVDD_OVDD GVDD_OVDD DRV_STD_MEM DRV_STD_MEM 8, 12 8, 12 DUART Control Signals SOUT1/PCI_CLK0 SIN1/PCI_CLK1 SOUT2/RTS1/ PCI_CLK2 SIN2/CTS1/ PCI_CLK3 T16 U16 W18 V19 Output I/O Output I/O GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD DRV_PCI_CLK DRV_PCI_CLK DRV_PCI_CLK DRV_PCI_CLK 5, 14 5, 14 5, 14 5, 14 Clock-Out Signals PCI_CLK0/SOUT1 PCI_CLK1/SIN1 PCI_CLK2/RTS1/ SOUT2 PCI_CLK3/CTS1/ SIN2 PCI_CLK4/DA3 PCI_SYNC_OUT PCI_SYNC_IN SDRAM_CLK[0:3] T16 U16 W18 V19 V17 U17 V18 D7 B7 C5 A5 Output I/O Output I/O Output Output Input Output Output Input Output Input GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD DRV_PCI_CLK DRV_PCI_CLK DRV_PCI_CLK DRV_PCI_CLK DRV_PCI_CLK DRV_PCI_CLK -- DRV_MEM_CTRL DRV_MEM_CTRL -- DRV_STD_MEM -- 5 15 1, 22 5, 14 5, 14 5, 14 5, 14 5, 14 SDRAM_SYNC_OUT B4 SDRAM_SYNC_IN CKO/DA1 OSC_IN A4 L1 R17 Miscellaneous Signals HRST_CTRL HRST_CPU MCP NMI SMI SRESET/SDMA12 TBEN/SDMA13 QACK/DA0 M2 L4 K4 M1 L2 L3 K3 A3 Input Input Output Input Input I/O I/O Output GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD -- -- DRV_STD_MEM -- -- DRV_MEM_CTRL DRV_MEM_CTRL DRV_STD_MEM 12 5, 12 5, 12 5, 10, 11 10, 11, 16 36 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Package Description Table 17. MPC8241 Pinout Listing (continued) Signal Name CHKSTOP_IN/ SDMA14 TRIG_IN/RCS2 TRIG_OUT/RCS3 MAA[0:2] MIV PMAA[0:1] PMAA[2] K2 P18 N18 E17 D17 C18 K1 N19 N17 M15 Package Pin Number Pin Type I/O I/O Output Output Output Output Output Power Supply GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD Output Driver Type DRV_MEM_CTRL -- DRV_STD_MEM DRV_STD_MEM DRV_STD_MEM DRV_STD_MEM DRV_STD_MEM Notes 5, 12 5, 12 5, 12 1, 10, 11 23 1, 2, 10, 11 1, 2, 11 Test/Configuration Signals PLL_CFG[0:4]/ DA[10:6] TEST0 DRDY RTC TCK TDI TDO TMS TRST N3 N2 N1 M4 M3 P16 P1 D13 T19 N15 T17 T18 R16 I/O Input Input Input Input Input Output Input Input GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD -- -- -- -- -- -- DRV_PCI -- -- 1, 5, 20 13, 21 5, 13 12 6, 13 6, 13 23 6, 13 6, 13 Power and Ground Signals GNDRING/GND F07 F08 F09 F10 F11 F12 F13 G07 G08 G09 G10 G11 G12 G13 H07 H08 H09 H10 H11 H12 H13 J07 J08 J09 J10 J11 J12 J13 K07 K08 K09 K10 K11 K12 K13 L07 L08 L09 L10 L11 L12 L13 M07 M08 M09 M10 M11 M12 M13 N07 N08 N09 N10 N11 N12 N13 P08 P09 P10 P11 P12 P13 R15 R18 U18 T1 U4 T6 W11 T14 Ground -- 17 LVDD Reference voltage 3.3 V, 5.0 V LVDD -- 37 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Package Description Table 17. MPC8241 Pinout Listing (continued) Signal Name GVDD_OVDD/ PWRRING Package Pin Number D09 D10 D11 E06 E07 E08 E09 E10 E11 E12 E13 E14 F06 F14 G06 G14 H06 H14 J06 J14 K06 K14 L06 L14 M06 M14 N06 N14 P06 P07 P14 R08 R09 R10 R11 R12 F03 H3 L5 N4 P5 V5 U8 W12 W16 R13 P19 L19 H19 F19 F15 C15 A13 A8 B5 A2 N5 W2 B1 M5 Pin Type Power for memory drivers and PCI/Stnd 3.3 V Power for core 1.8 V -- Power for PLL (CPU core logic) 1.8 V Power for PLL (peripheral logic) 1.8 V Power Supply GVDD_OVDD Output Driver Type -- Notes 18 VDD VDD -- No Connect AVDD -- AVDD -- -- AVDD2 R14 AVDD2 -- Debug/Manufacturing Pins DA0/QACK DA1/CKO DA2 DA3/PCI_CLK4 DA4/REQ4 DA5/GNT4 DA[10:6]/ PLL_CFG[0:4] DA[11] DA[12:13] A3 L1 R5 V17 W13 T11 N3 N2 N1 M4 M3 T13 M16 N16 Output Output Output Output I/O Output I/O Output Output GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD GVDD_OVDD DRV_STD_MEM DRV_STD_MEM DRV_PCI DRV_PCI_CLK -- DRV_PCI -- DRV_PCI DRV_STD_MEM 5, 10, 11 5 19 5 5, 6 2, 4, 5 1, 5, 20 1, 19 19 38 MPC8241 Integrated Processor Hardware Specifications MOTOROLA PLL Configuration Table 17. MPC8241 Pinout Listing (continued) Signal Name DA[14:15] Package Pin Number B6 D8 Pin Type Output Power Supply GVDD_OVDD Output Driver Type DRV_MEM_CTRL Notes 1, 19 Notes: 1. Multi-pin signals such as AD[31:0] or MDL[0:31] have their physical package pin numbers listed in order corresponding to the signal names. Ex: AD0 is on pin U1, AD1 is on pin U2,..., AD31 is on pin U13. 2. This pin is affected by programmable PCI_HOLD_DEL parameter. 3. Recommend a weak pull-up resistor (2-10 k) be placed on this PCI control pin to LVDD. 4. GNT4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC8241 is in the reset state. 5. This pin is a multiplexed signal and appears more than once in this table. 6. This pin has an internal pull-up resistor which is enabled at all times. The value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 7. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification (Rev. 2.2). 8. This pin is an open drain signal. 9. DL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC8241 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset. 10. This pin has an internal pull-up resistor which is enabled only when the MPC8241 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset. 11. This pin is a reset configuration pin. 12. Recommend a weak pull-up resistor (2-10 k) be placed on this pin to GVDD_OVDD. 13. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3. 14. External PCI clocking source or fanout buffer may be required for system if using the MPC8241 DUART functionality since PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode. 15. OSC_IN utilizes the 3.3-V PCI interface driver which is 5-V tolerant, see Table 2 for details. 16. This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open drain. 17. All grounded pins are connected together; connections should not be made to individual pins. The list represents the balls that are connected to Ground. 18. GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset. Note that GVDD_OVDD pins are all shorted together, PWRRING. The list represents the balls that are connected to PWRRING. Connections should not be made to individual PWRRING pins. 19. Treat these pins as No Connects unless using debug address functionality. 20. PLL_CFG signals must be driven on reset. 21. Place a pull-up resistor of 120 or less on the TEST0 pin. 22. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals use DRV_MEM_CLK for chip Rev 1.2B. 23. The driver capability of this pin is hardwired to 40 and cannot be changed. 1.6 PLL Configuration The internal PLLs of the MPC8241 are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the MPC8241 is shown in Table 18 and Table 19. 39 MPC8241 Integrated Processor Hardware Specifications MOTOROLA PLL Configuration Table 18. PLL Configurations for the 166 and 200 MHz parts of MPC8241 166 MHz-Part 2 PCI Clock Input (PCI_ SYNC_IN) Range 3 (MHz) Periph Logic/ Mem Bus Clock Range (MHz) 200-MHz Part 2 PCI Clock Input (PCI_ SYNC_IN) Range 3 (MHz) 25-265 153-166 100-132 100-164 150-165 344-445 507-663 25-448,10 60-663 Periph Logic/ Mem Bus Clock Range (MHz) 75-78 34-44 50-66 50-88 60-66 Bypass 150-166 504-663 50-66 150-198 Multipliers Ref 2 PLL_ CFG [0:4] 1 CPU Clock Range (MHz) CPU Clock Range (MHz) PCI-toMem-toMem CPU (Mem VCO) (CPU VCO) 0 2 3 4 5 6 7 Rev B 00000 00010 000116 00100 001016 001109 001116 00111 01000 01001 01011 01100 01110 10000 10010 10100 10110 10111 11001 11010 11011 11100 11101 1111014 445,13 335,13 374-415 304-335 25-275 25-275,11 504-555 504-55 5 344-375 507-663 25-415 60-663 Not available 34-37 50-66 50-82 60-66 Bypass 50-55 188-195 153-200 100-132 100-176 150-165 3 (2) 1 (4) 1 (Bypass) 2 (4) 1 (Bypass) Bypass 1 (Bypass) 2.5 (2) 4.5 (2) 2 (4) 2 (4) 2.5 (2) Bypass 3 (2) 7 Rev D Not available 50-55 76-82 150-166 152-164 504-663 384-505,12 445 150-165 150-162 150-166 150-166 304-405 25-335 25-335,12 504-663 25-285 255 255 66 37-41 Not available 165 150-166 3313-405 374-505 335,13 445,13 66 Not usable 166 4413-535 50-66 76-100 66 60-80 60-66 75-100 75-99 50-56 50 100 66-80 37-50 66 66 66-80 Not usable 150-198 152-200 198 150-200 150-198 150-200 150-198 175-196 200 200 165-200 150-200 198 198 165-200 1 (4) 2 (2) 2(2) 2 (4) 2 (4) 3 (2) 1.5 (2) 2 (4) 2(4) 4(2) 2(2) 1 (4) 2(2) 1.5(2) 1.5 (2) Off 3 (2) 2 (2) 2.5(2) 2.5 (2) 3 (2) 2 (2) 2 (2) 3.5 (2) 4(2) 2(2) 2.5(2) 4 (2) 3(2) 3(2) 2.5 (2) Off 8 9 B C E 10 12 14 16 17 19 1A 1B 1C 1D 1E 384-415,11 Not available 60-66 50-54 75-83 75-83 504-555,11 Not available 40 MPC8241 Integrated Processor Hardware Specifications MOTOROLA PLL Configuration Table 18. PLL Configurations for the 166 and 200 MHz parts of MPC8241 (continued) 166 MHz-Part 2 PCI Clock Input (PCI_ SYNC_IN) Range 3 (MHz) Periph Logic/ Mem Bus Clock Range (MHz) Not usable 200-MHz Part 2 PCI Clock Input (PCI_ SYNC_IN) Range 3 (MHz) Periph Logic/ Mem Bus Clock Range (MHz) Not usable Multipliers Ref 2 PLL_ CFG [0:4] 1 CPU Clock Range (MHz) CPU Clock Range (MHz) PCI-toMem-toMem CPU (Mem VCO) (CPU VCO) 1F 1111114 Off Off Notes: 1. PLL_CFG[0:4] settings not listed are reserved. Bits 7-4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value. Note the impact of the relevant revisions for mode 7. 2. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 3. Limited by maximum PCI input frequency (66 MHz). 4. Limited by minimum CPU VCO frequency (300 MHz). 5. Limited by maximum CPU operating frequency. 6. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode. 7. Limited by minimum CPU operating frequency (100 MHz). 8. Limited due to maximum memory VCO frequency (352 MHz). 9. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in dual PLL bypass mode. 10. Limited by maximum CPU VCO frequency (704 MHz). 11. Limited by maximum system memory interface operating frequency (83 MHz @ 166 MHz CPU bus speed). 12. Limited by maximum system memory interface operating frequency (100 MHz @ 200 MHz CPU bus speed). 13. Limited by minimum memory VCO frequency (132 MHz). 14. In clock off mode, no clocking occurs inside the MPC8241 regardless of the PCI_SYNC_IN input. Table 19. PLL Configurations (266-MHz Parts) 266-MHz Part 9 Ref 2 PLL_ CFG[0:4] 10,13 PCI Clock Input (PCI_SYNC_IN) Range 1 (MHz) 25-355 25-295 5018-595 5017-661 25-444 Periph Logic/ Mem Bus Clock Range (MHz) 75-105 75-88 50-59 50-66 50-88 Reserved Bypass CPU Clock Range (MHz) 188-263 225-264 225-266 100-133 100-176 Multipliers PCI-toMem-toMem CPU (Mem VCO) (CPU VCO) 3 (2) 3 (2) 1 (4) 1 (Bypass) 2 (4) Note 20 Bypass 2.5 (2) 3 (2) 4.5 (2) 2 (4) 2 (4) 0 1 2 3 4 5 6 0000012 0000112 0001011 0001111,14 0010012 00101 0011015 41 MPC8241 Integrated Processor Hardware Specifications MOTOROLA PLL Configuration Table 19. PLL Configurations (266-MHz Parts) (continued) 266-MHz Part 9 Ref 2 PLL_ CFG[0:4] 10,13 PCI Clock Input (PCI_SYNC_IN) Range 1 (MHz) 506-661 Periph Logic/ Mem Bus Clock Range (MHz) 50-66 CPU Clock Range (MHz) 150-198 Not Available 50 -66 6 1 Multipliers PCI-toMem-toMem CPU (Mem VCO) (CPU VCO) 1 (Bypass) 3 (2) 7 (Rev B) 7 (Rev D) 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E (Rev B) 1E (Rev D) 0011114 0011114 01000 12 50-66 76-132 50-58 68-88 60-88 68-75 50-88 75 75-132 100-106 75-99 Not available 150-198 152-264 225-261 204-264 150-220 238-263 150-264 263 150-264 250-266 150-198 1 (4) 2 (2) 2 (4) 1.5 (2) 2 (4) 1.5 (2) 2 (4) 3 (2) 3 (2) 4 (2) 1.5 (2) 4 (2) 3 (2) 2 (2) 4.5 (2) 3 (2) 2.5 (2) 3.5 (2) 3 (2) 3.5 (2) 2 (2) 2.5 (2) 2 (2) 3 (2) 3.5 (2) 4 (2) 4 (2) 2 (2) 3 (2) 2.5 (2) 4 (2) 3 (2) 3 (2) 2.5 (2) Off 3.5(2) 0100119 01010 12 386-661 25-29 5 0101119 0110012 0110119 0111012 0111119 1000012 1000119 1001012 1001119 1010012 1010119 1011012 1011119 1100012 1100119 1101012 1101119 1110012 1110112 111108 11110 453-595 306-444 453-505 25-445 255 25-4416,5 25-265 506-661 25-385 50-76 Not available 175-266 2 (4) 2.5 (2) 25-335 25-335 273-355 333-535 5018-661 343-445 443-595 443-661 50-66 100-132 68-88 66-106 50-66 68-88 66-88 66-99 Not usable 200-264 200-264 204-264 165-265 200-264 204-264 198-264 165-248 2 (4) 4 (2) 2.5 (2) 2 (2) 1 (4) 2 (2) 1.5 (2) 1.5 (2) Off 333-385 66-76 231-266 2(2) 42 MPC8241 Integrated Processor Hardware Specifications MOTOROLA PLL Configuration Table 19. PLL Configurations (266-MHz Parts) (continued) 266-MHz Part 9 Ref 2 PLL_ CFG[0:4] 10,13 PCI Clock Input (PCI_SYNC_IN) Range 1 (MHz) Periph Logic/ Mem Bus Clock Range (MHz) Not usable CPU Clock Range (MHz) Multipliers PCI-toMem-toMem CPU (Mem VCO) (CPU VCO) Off Off 1F 111118 Notes: 1. Limited by maximum PCI input frequency (66 MHz). 2. Note the impact of the relevant revisions for modes 7 and 1E. 3. Limited by minimum memory VCO frequency (132 MHz). 4. Limited due to maximum memory VCO frequency (352 MHz). 5. Limited by maximum CPU operating frequency. 6. Limited by minimum CPU VCO frequency (300 MHz). 7. Limited by maximum CPU VCO frequency (704 MHz). 8. In clock off mode, no clocking occurs inside the MPC8241 regardless of the PCI_SYNC_IN input. 9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 10. PLL_CFG[0:4] settings not listed are reserved. 11. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not backwards-compatible. 12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully backwards-compatible. 13. Bits 7-4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value. 14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode. 15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in dual PLL bypass mode. 16. Limited by maximum system memory interface operating frequency (133 MHz @ 266 MHz CPU). 17. Limited by minimum CPU operating frequency (100 MHz). 18. Limited by minimum memory bus frequency (50 MHz). 19. PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the MPC8240 and may not be fully backwards-compatible. 20. No longer supported. 43 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information 1.7 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8241. 1.7.1 PLL Power Supply Filtering The AVDD and AVDD2 power signals are provided on the MPC8241 to provide power to the peripheral logic/memory bus PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the AVDD and AVDD2 input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 27 using surface mount capacitors with minimum effective series inductance (ESL) is recommended for AVDD and AVDD2 power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over using multiple values. The circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important. VDD 10 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDD or AVDD2 GND Figure 27. PLL Power Supply Filter Circuit 1.7.2 Power Supply Sizing The power consumption numbers provided in Table 5 do not reflect power from the GVDD_OVDD power supply which are non-negligible for the MPC8241. 1.7.3 Decoupling Recommendations Due to its dynamic power management feature, the large address and data buses, and its high operating frequencies, the MPC8241 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8241 system, and the MPC8241 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, GVDD_OVDD, and LVDD pin of the MPC8241. It is also recommended that these decoupling capacitors receive their power from dedicated power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the length of the part. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, GVDD_OVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two 44 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information vias to minimize inductance. Suggested bulk capacitors: 100-330 F (AVX TPS tantalum or Sanyo OSCON). 1.7.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active-low inputs should be tied to OVDD. Unused active-high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD_OVDD, LVDD, and GND pins of the MPC8241. The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to the PCI_SYNC_IN input of the MPC8241. The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then returned to the SDRAM_SYNC_IN input of the MPC8241. The trace length may be used to skew or adjust the timing window as needed. See Motorola application notes AN1849/D, MPC107 Design Guide, and AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines, for more information on this topic. Note that there is an SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see Table 10). 1.7.5 Pull-Up/Pull-Down Resistor Requirements The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7]. If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31] and PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not require pull-up resistors and should be left unconnected by the system to minimize possible output switching. The TEST0 pin requires a pull-up resistor of 120 or less connected to GVDD_OVDD. It is recommended that RTC have weak pull-up resistors (2-10 k) connected to GVDD_OVDD. It is recommended that the following signals be pulled up to GVDD_OVDD with weak pull-up resistors (2-10 k): SDA, SCL, SMI, SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2, and DRDY. It is recommended that the following PCI control signals be pulled up to LVDD with weak pull-up resistors (2-10 k): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI, TMS, and TRST. See Table 17 for more information. The following pins have internal pull-up resistors enabled only while device is in the reset state: GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], PMAA[0:2], and QACK/DA0. See Table 17 for more information. The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP, QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks after the negation of HRST_CPU and HRST_CTRL. 45 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information Reset configuration pins should be tied to GND via 1-k pull-down resistors to ensure a logic zero level is read into the configuration bits during reset if the default logic-one level is not desired. Any other unused active low input pins should be tied to a logic-one level via weak pull-up resistors (2-10 k) to the appropriate power supply listed in Table 17. Unused active high input pins should be tied to GND via weak pull-down resistors (2-10 k). 1.7.6 PCI Reference Voltage--LVDD The MPC8241 PCI reference voltage (LVDD) pins should be connected to 3.3 0.3 V power supply if interfacing the MPC8241 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to 5.0 V 5% power supply if interfacing the MPC8241 into a 5-V PCI bus system. For either reference voltage, the MPC8241 always performs 3.3-V signaling as described in the PCI Local Bus Specification (Rev. 2.2). The MPC8241 tolerates 5-V signals when interfaced into a 5-V PCI bus system. (See Errata No. 18 in the MPC8245/MPC8241 Integrated Processor Chip Errata). 1.7.7 JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 28 allows the COP to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted ensuring that the JTAG scan chain is initialized during power-on. The COP header shown in Figure 28 adds many benefits--breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface--and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). There is no standardized way to number the COP header shown in Figure 28; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 28 is common to all known emulators. 46 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information MPC8241 From Target Board Sources (if any) SRESET HRESET 5 SRESET 5 HRST_CPU 10 k HRST_CTRL OVDD OVDD 10 k OVDD 10 k 13 11 HRESET SRESET 5 1 3 5 7 9 11 2 4 6 8 OVDD 4 6 5 2 TRST VDD_SENSE 1 k 10 k TRST 10 k 10 k 10 k CHKSTOP_IN OVDD OVDD OVDD OVDD CHKSTOP_IN 6 TMS 10 15 3 12 KEY 13 No pin Key 14 4 COP Header 8 TMS 9 1 3 TCK 7 2 10 12 16 NC NC NC TDO TDI 15 16 COP Connector Physical Pin Out TDO TDI TCK QACK 1 Notes: 1. QACK is an output on the MPC8241 and is not required at the COP header for emulation. 2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the MPC8241. Connect pin 5 of the COP header to OVDD with a 1-k pull-up resistor. 3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the MPC8241 Connect pin 15 of the COP header to OVDD with a 10-k pull-up resistor. 4. Pin 14 is not physically present on the COP header. 5. SRESET functions as output SDMA12 in extended ROM mode. 6. CHKSTOP_IN functions as output SDMA14 in extended ROM mode. Figure 28. COP Connector Diagram 47 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information 1.7.8 Thermal Management Information This section provides thermal management information for the plastic ball grid array (PBGA) package for air-cooled applications. Depending on the application environment and the operating frequency, a heat sink may be required to maintain junction temperature within specifications. Proper thermal control design is primarily dependent on the system-level design: heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, or mounting clip and screw assembly; see Figure 29. Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material PBGA Package Wire Die Printed-Circuit Board Option Figure 29. Package Exploded Cross-Sectional View with Several Heat Sink Options Figure 30 depicts the die junction-to-ambient thermal resistance for four typical cases: * * * * A heat sink is not attached to the PBGA package and there exists a high board level thermal loading from adjacent components. (Label used--1s.) A heat sink is not attached to the PBGA package and there exists a low board level thermal loading from adjacent components. (Label used--2s2p.) A large heat sink (cross cut extrusion, 38 x 38 x 16.5 mm) is attached to the PBGA package and there exists high board level thermal loading from adjacent components. (Label used--1s/sink.) A large heat sink (cross cut extrusion, 38 x 38 x 16.5 mm) is attached to the PBGA package and there exists low board level thermal loading from adjacent components. (Label used--2s2p/sink.) 48 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information Die Junction-to-Ambient Thermal Resistance (C/W) 50.0 40.0 1s 30.0 20.0 10.0 0.0 0 0.5 1 1.5 2 2.5 2s 2p 1s /sink 2s 2p/s ink Airflow Velocity (m/s) Figure 30. Die Junction-to-Ambient Resistance The board designer can choose between several types of heat sinks to place on the MPC8241. There are several commercially available heat sinks for the MPC8241 provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 603-224-9988 408-749-7601 818-842-7277 800-522-6752 603-635-5102 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Other heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow. 49 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information 1.7.8.1 Internal Package Conduction Resistance For the PBGA, die-up, packaging technology, shown in Figure 29, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case thermal resistance The die junction-to-ball thermal resistance Figure 31 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed-Circuit Board External Resistance Radiation Convection (Note the internal versus external package resistance) Figure 31. PBGA Package with Heat Sink Mounted to a Printed-Circuit Board For this die-up, wire-bond PBGA package, heat generated on the active side of the chip is conducted mainly through the mold cap, the heat sink attach material (or thermal interface material), and finally through the heat sink where it is removed by forced-air convection. 1.7.8.2 Adhesives and Thermal Interface Materials A thermal interface material is recommended between the top of the mold cap and the bottom of the heat sink to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 32 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 29). Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors: thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. 50 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information 2 Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Specific Thermal Resistance (K-in.2/W) 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 32. Thermal Performance of Select Thermal Interface Material The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01888-4014 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dow.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com 800-347-4572 781-935-4850 800-248-2481 888-642-7674 51 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 888-246-9050 1.7.8.3 Heat Sink Usage TJ = TA + (RJA x PD) An estimation of the chip junction temperature, TJ, can be obtained from the equation: where: TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, two values are in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single-layer board is appropriate for the tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the airflow around the device, the interface material, the mounting arrangement on the printed-circuit board, or the thermal dissipation on the printed-circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature atop the package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 52 MPC8241 Integrated Processor Hardware Specifications MOTOROLA System Design Information When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. In many cases, it is appropriate to simulate the system environment using a computational fluid dynamics thermal simulation tool. In such a tool, the simplest thermal model of a package which has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. 1.7.9 References Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 53 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Document Revision History 1.8 C Document Revision History Table 20. Revision History Table Substantive Change(s) Initial release. Updated Features list in Section 1.2. Corrected pin assignments in Table 16 for DA[15] and DQM[3] signals. Added vendor (Cool Innovations, Inc.) to list of heat sink vendors. Table 16--Corrected pin number for PLL_CFG0/DA10 to N3. The pin was already correctly listed for DA10/PLL_CFG0. Updated note 1 to reflect pin assignments for the MPC8241. Updated footnotes throughout document. Section 1.4.3.3--Updated note 4 to correct bit values of PCI_HOLD_DEL in PMCR2. Section 1.6--Updated notes in Table 17. Included memory VCO minimum and maximum numbers. Section 1.7.8--Updated description of bits PCI_HOLD_DEL in PMCR2. Section 1.7.10.3--Replaced thermal characterization parameter (YJT) with correct thermal characterization parameter (JT). Changed symbol to JT. Corrected solder ball information in Section 1.5.1 to 62 Sn/36 Pb/2 Ag. Section 1.4.3.1--Corrected DLL_EXTEND labeling in Figures 5 through 8. Removed note for pin TRIG_OUT/RCS3 in Table 16, as well as from the list of pins needing to be pulled up to IVDD in Section 1.7.6. Corrected order information labeling in Section 1.9 to MPC8241XZPXXXX. Also corrected label description of ZU=PBGA to ZP=PBGA. Updated document template. Section 1.4.1.5--Updated driver type names in Table 4 so that they are consistent with the driver types referred to in the MPC8245 Integrated Processor User's Manual. Added notes 5 and 6 to Table 4. Section 1.4.3.1--Added reference to AN2164 in note 7. Labeled N value in Figures 5 through 8. Section 1.4.3.2--Updated Figure 9 to show Tos. Table 9--Changed default for 0x77 bits 5:4 to 0b10. Section 1.4.3.3--Added item 12e to Table 10 for SDRAM_SYNC_IN to Output Valid Timing. Updated Figure 13 to state GVdd_OVdd instead of OVdd. Section 1.5.3--Updated driver type names to match those used in Table 4. Updated notes for the following signals: DRDY, SDRAM_CLK[0:3], MIV, RTC, TDO, and DA[11]. Section 1.6--Updated PLL table and notes. Removed old Section 1.7.2 on voltage sequencing requirements. Added cautions regarding voltage sequencing to the end of Table 2 in Section 1.4.1.2. Section 1.7.3--Changed sentence recommendation regarding decoupling capacitors. Section 1.7.5--Added reference to AN2164. Section 1.7.6--Added sentence regarding the PLL_CFG signals. Removed old Section 1.7.8 since the MPC8241 cannot be used as a drop in replacement for the MPC8240 because of pin compatibility issues. Section 1.7.8--Updated TRST information in this section and Figure 26. Section 1.7.9--Updated list for heat sink and thermal interface vendors. Section 1.9--Changed format of ordering information section. Added tables to reflect part number specifications also available. Added Sections 1.9.2 and 1.9.3. Table 20 provides a revision history for this hardware specification. Rev. No. 0 0.1 0.2 0.3 1 54 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Ordering Information Table 20. Revision History Table Rev. No. 2 Substantive Change(s) Section 1.4.1.2--Updated note 1 to include 266-MHz part. Added a line to cautions 2 and 3 in the notes section of Table 2. Added Figures 4 and 5 to show the overshoot and undershoot requirements for the PCI interface. Section 1.4.1.3--Table 3: Updated minimum value for input high voltage, and maximum value for capacitance. Section 1.4.3.2--Appended Figures 9 and 10. Section 1.4.3.4--Added a column to Table 13 to include 133-MHz memory bus speed for 266-MHz part. Section 1.5.2--Changed Figure 24 to accommodate new package offerings. Section 1.6--Added Table 19 for PLL of the 266-MHz part. Section 1.7.7--Corrected note numbering in COP connector diagram. Section 1.9.1--Updated package description in part marking nomenclature. Section 1.4.1.2--Changed recommended value in Table 2 for I/O buffer supply to 3.3 0.3 V. Changed wording referencing Figure 4 to refer to the MPC8241. Section 1.4.2--Table 6: Updated values for thermal characterization data as per the new packaging and 266-MHz part. Added note 7 for the difference between 166/200 MHz and the 266-MHz packaging. Section 1.4.3--Corrected the voltage listing for the 266 MHz to 1.8 0.1 V in Table 7. Section 1.5--Changed package parameters and illustration based on new packaging. Section 1.6--Table 18: Modified PLL configuration for 166- and 200-MHz parts for Mode 7 to specify that this mode is not available for Rev . D of the part. Added sentence to note 1 referencing update for Mode 7. Table 19: Made several range updates for various modes to accommodate VCO limits. Added Mode 7 and 1E updates for Rev. D. Updated VCO limits listed in notes 4, 6, and 7. 3 1.9 Ordering Information Ordering information for the parts fully covered by this document is provided in Section 1.9.1, "Part Numbers Fully Addressed by This Document." Section 1.9.2, "Part Numbers Not Fully Addressed by This Document," lists the part numbers which do not fully conform to the specifications of this document. These special part numbers require an additional document called a part number specification. 1.9.1 Part Numbers Fully Addressed by This Document Table 21 provides the Motorola part numbering nomenclature for the MPC8241. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number.The revision level can be determined by reading the Revision ID register at address offset 0x08. 55 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Ordering Information Table 21. Part Numbering Nomenclature XPC Product Code MPC nnnn Part Identifier 8241 L Process Descriptor L = Standard Spec. 1.8 V 100 mV 0 to 105C xx Package 1 ZQ = thick substrate and thick mold cap PBGA VR = Lead free version of package nnn Processor Frequency 2 166 MHz 200 MHz 266 MHz x Revision Level Contact local Motorola Sales Office Notes: 1. See Section 1.5, "Package Description," for more information on available package types. 2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies. 1.9.2 Part Numbers Not Fully Addressed by This Document Parts with application modifiers or revision levels not fully addressed in this specification document are described in separate part number specifications which supplement and supersede this document; see Table 22. Table 22. Part Numbers with Separate Documentation Part Number Series XPC8241TZPnnnx Operating Conditions 1.8 V 100 mV, -40 to 105C 166 MHz, 200 MHz, 266 MHz Document Order Number of Applicable Specification MPC8241TZPPNS/D Note: For other differences, see applicable specifications. 56 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Ordering Information 1.9.3 Part Marking Parts are marked as the example shown in Figure 33. MPC8241L xx266x MMMMMM ATWLYYWWA 8241 PBGA Notes: MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 33. Part Marking for PBGA Device 57 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK 58 MPC8241 Integrated Processor Hardware Specifications MOTOROLA Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK 59 MPC8241 Integrated Processor Hardware Specifications MOTOROLA HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: (800) 521-6274 HOME PAGE: www.motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003 MPC8241EC/D |
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